1. Field of the Invention
The present invention relates to an apparatus for increasing the data transfer rate of a computer. More particularly, the invention relates to an apparatus for smoothly multiplying the frequency of a basic clock of the computer during a burst transfer cycle and smoothly resuming the basic clock frequency upon completing the burst transfer cycle.
2. Description of the Related Art
The personal computer industry is evolving quickly due to the user's demands for faster, smaller, and more powerful computers. To flexibly accommodate the needs of a variety of applications, a personal computer typically has an expansion bus such as an extended industry standard architecture (EISA) bus for interfacing the microprocessor with one or more optional external plug-in logic circuit boards.
Derived from the original industry standard architecture (ISA) standard which is still in use today, all EISA performance and function enhancements are superset features of the ISA bus standard. The EISA specification provides for a variety of cycle types to cover the range of speed and complexity requirements for different applications. The EISA bus specification describes all parameters that must be followed for any device to communicate with an EISA bus and is fully disclosed in Appendix A of U.S. Pat. No. 5,101,492, hereby incorporated by reference.
Under the EISA specification, the standard EISA transfer cycle requires two clock cycles. However, bus masters are permitted to generate EISA burst cycles which require only one clock per transfer after the first cycle. The burst transfer cycle allows a master running at the full data rate to transfer one 32-bit data element on every rising edge of the bus clock (BCLK), whose frequency is typically 8 to 8.3 MHz. At an 8.3 MHz BCLK frequency, the computer system can burst transfer data with up to a 33 megabytes per second transfer rate.
The EISA standard has recently been extended to include two new burst transfer modes called the enhanced master burst (EMB) transfer modes. The first extension, known as the EMB66 protocol, provides up to a two-fold increase in the data transfer rate when compared to existing EISA bus master burst rates while maintaining the existing bus clock frequency. The second extension, known as the EMB133 protocol, provides up to a four-fold increase in data transfer rate. The two-fold performance increase in the EMB66 protocol is achieved by transferring one 32-bit data element on each of the rising and falling edges of the BCLK, thus transferring up to 66 megabytes per second.
The EMB133 protocol extends this performance improvement one step further by transferring 64-bits of data on each of the rising and falling edges of BCLK. The EMB133 protocol uses the EISA address and byte enable lines for data transfer in addition to the existing data bus to effectively increase the width of each EISA data transfer from 32-bits wide to 64-bits wide. As all data operandi consist of 64 bits in the EMB133 mode, the EMB133 transfer protocol can thus transfer burst cycles with up to 133 megabytes per second data transfer rate. As can be seen, the newly defined EMB extensions to the EISA bus specification provide for increasing the burst transfer rate of EISA bus masters.
Since data are transferred twice as fast in the EMB66 mode, a need exists for a clock generator that can automatically multiply the basic clock frequency to handle the increase in the data transfer rate and automatically return to the basic clock frequency upon completing the burst mode transfer. Further, since some circuits depend on the timing relationship with respect to the falling and/or rising edges of the basic clock, a need exists for a clock generator that can smoothly traverse the basic and the multiplied clock frequency while maintaining the edge alignments with respect to the basic clock.